Oxide-nitride stack gate dielectric
US8445381B2 · kind B2 · utility
4Cited by
89References
8Claims
0Family size
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Key dates
| Filing date | Dec 20, 2007 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Jul 11, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02233
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.