Thermal enhancement for multi-layer semiconductor stacks
US8445918B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2010 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Feb 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement and method in one aspect utilize thermal-only through vias, extending between the opposing faces of stacked semiconductor dies, to increase the thermal conductivity of a multi-layer semiconductor stack. The thermal vias are provided in addition to data-carrying through vias, which communicate data signals between circuit layers, and power-carrying through vias, which are coupled to a power distribution network for the circuit layers, such that the thermal conductivity is increased above that which may be provided by the data-carrying and power-carrying through vias in the stack. A circuit arrangement and method in another aspect organize the circuit layers in a multi-layer semiconductor stack based upon current density so as to reduce power distribution losses in the stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.