Logic-cell-compatible decoupling capacitor

US8446175B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventor

• Thomas J. Aton · Dallas, US

Key dates

• Filing date: Feb 22, 2011
• Grant date: May 21, 2013
• Expiry date: Feb 22, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10

Abstract

An integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates. A process of forming an integrated circuit containing CMOS logic gates and a logic-cell-compatible decoupling capacitor adjacent to the logic gates, in which the decoupling capacitor includes p+/n and n+/p capacitors, resistors between 1 and 1000 ohms connecting the capacitors to Vdd and Vss buses, and gate elements which have widths and spacings similar to the adjacent logic gates.