Methods of making a semiconductor memory device
US8446762B2 · kind B2 · utility
1Cited by
233References
28Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 25, 2011 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Mar 25, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.