Method for operating a flash memory device
US8446778B2 · kind B2 · utility
4Cited by
0References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 31, 2009 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Dec 10, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A charge trap flash memory device is capable of preventing a data retention fail by ensuring a data retention margin. A method for operating the charge trap flash memory device is provided. A selected memory cell is programmed using a program voltage. The selected memory cell is verified using a first program verify voltage. Date retention states of selected memory cell having passed the program verify step are verified using a retention verify voltage. A read step of determining a program pass or fail by reading data of the selected memory cell having passed the retention verify step is performed using a read voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.