Estimation and compensation of clock variation in received signal
US8447004B2 · kind B2 · utility
1Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2011 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Jan 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/044
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and system for estimating and compensating for variation between a receiver clock and a transmitter clock, where a receiver utilizes a high frequency clock signal to generate a receiver clock and then adjusts the receiver clock to compensate for variations between the receiver and transmitter clocks. The adjusted receiver clock is used to sample nibble pulses in a received data frame. Counter based compensation of the receiver clock eliminates the need for the receiver to perform floating point calculations, improves the accuracy of nibble pulse sampling and also reduces area and power consumption of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.