Generating simulation code from a specification of a circuit design
US8447581B1 · kind B1 · utility
1Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2009 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Dec 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
During the elaboration and synthesis of a circuit design, a parse tree generally must be fully expanded to access memory resources and data of individual module instances in order to perform optimizations that will result in better runtime performance of generated simulation code. The present invention reduces memory requirements in generating simulation or emulation executable code by implementing a collapsed parse tree, where multiple instances of a module in a HDL design are represented by a single representative node in the parse tree.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.