Hash processing using a processor
US8447988B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2009 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Sep 16, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/125
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In certain embodiments, a digital signal processor (DSP) has multiple arithmetic logic units and a register module. The DSP is adapted to generate a message digest H from a message M in accordance with the SHA-1 standard, where M includes N blocks M(i), i=1, . . . , N, and the processing of each block M(i) includes t iterations of processing words of message schedule {Wt}. In each iteration possible, the DSP uses free operations to precalculate Wt and working variable values for use in the next iteration. In addition, in each iteration possible, the DSP rotates the registers associated with particular working variables to reduce operations that merely copy unchanged values from one register to another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.