Clustering and fanout optimizations of asynchronous circuits
US8448105B2 · kind B2 · utility
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Inventors
Key dates
| Filing date | Apr 24, 2009 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Oct 24, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are described for generating asynchronous circuits from any arbitrary HDL representation of a synchronous circuit by automatically clustering the synthesized gates into pipeline stages that are then slack-matched to meet performance goals while minimizing area. Automatic pipelining can be provided in which the throughput of the overall design is not limited to the clock frequency or the level of pipelining in the original RTL specification. The techniques are applicable to many asynchronous design styles. A model and infrastructure can be designed that guides clustering to avoid the introduction of deadlocks and achieve a target circuit performance. Slack matching models can be used to take advantage of fanout optimizations of buffer trees that improve the quality of the results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.