Method for dual edge clock and buffer tree synthesis
US8448114B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2012 |
| Grant date | May 21, 2013 |
| Priority date | — |
| Expiry date | Jan 23, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for balancing both edges of a signal of an integrated circuit (IC) design includes defining a virtual cell to have the same geometry as that of a port of the IC design. First and second input pins of the virtual cell are defined for detecting rising and falling edges. The first and second input pin geometries are defined to be the same as that of the corresponding pins of the port. The virtual cell is overlapped with the port so the first and second input pins are connected to the corresponding port network. The first and second input pins are configured as sinks for clock and buffer tree synthesis. An EDA tool identifies the first and second input pins as additional parallel sinks on the port network and balances the rising and falling edges of the signal at the port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.