Method for introducing channel stress and field effect transistor fabricated by the same
US8450155B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2011 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | May 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/015
Abstract
The present invention relates to CMOS ultra large scale integrated circuits, and provides a method for introducing channel stress and a field effect transistor fabricated by the same. According to the present invention, a strained dielectric layer is interposed between source/drain regions and a substrate of a field effect transistor, and a strain is induced in a channel by the strained dielectric layer which directly contacts the substrate, so as to improve a carrier mobility of the channel and a performance of the device. The specific effects of the invention include: a tensile strain may be induced in the channel by using the strained dielectric layer having a tensile strain in order to increase an electron mobility of the channel; a compressive strain may be induced in the channel by using the strained dielectric layer having a compressive strain in order to increase a hole mobility of the channel. According to the invention, not only an effectiveness of the introduction of channel stress is ensued, but the device structure of the field effect transistor is also improved fundamentally, so that a capability for suppressing a short channel effect of the device is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.