Method of reducing floating body effect of SOI MOS device via a large tilt ion implantation

US8450195B2 · kind B2 · utility

Assignee

• SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY CHINESE ACADEMY OF SCIENCES · CN

Inventors

• Jing Chen · Shanghai, CN
• Xiaolu Huang · Shanghai, CN
• Jiexin Luo · Shanghai, CN
• Qingqing Wu · Shanghai, CN
• Xi Wang · Shanghai, CN

Key dates

• Filing date: Jul 14, 2010
• Grant date: May 28, 2013
• Expiry date: Jul 14, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present invention discloses a method of reducing floating body effect of SOI MOS device via a large tilt ion implantation including a step of: (a) implanting ions in an inclined direction into an NMOS with a buried insulation layer forming a highly doped P region under a source region of the NMOS and above the buried insulation layer, wherein the angle between a longitudinal line of the NMOS and the inclined direction is ranging from 15 to 45 degrees. Through this method, the highly doped P region under the source region and a highly doped N region form a tunnel junction so as to reduce the floating body effect. Furthermore, the chip area will not be increased, manufacturing process is simple and the method is compatible with conventional CMOS process.