Contact elements of a semiconductor device formed by electroless plating and excess material removal with reduced sheer forces
US8450197B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2010 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | Jan 12, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76879
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Contact elements in the contact level of a semiconductor device may be formed on the basis of a selective deposition technique, such as electroless plating, wherein an efficient planarization of the contact level is achieved without subjecting the contact elements to undue mechanical stress. In some illustrative embodiments, an overfilling of the contact openings may be reliably avoided and the planarization of the surface topography is accomplished on the basis of a non-critical polishing process. In other cases, electrochemical etch techniques are applied in combination with a conductive sacrificial current distribution layer in order to remove any excess material of the contact elements without inducing undue mechanical stress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.