Method of forming MOS transistors including SiON gate dielectric with enhanced nitrogen concentration at its sidewalls
US8450221B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2010 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | Nov 7, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ≧ the N concentration in a bulk of the annealed N-enhanced SiON gate layer −2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.