Clock synchronization in a memory system
US8451674B2 · kind B2 · utility
3Cited by
40References
22Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 13, 2012 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | Apr 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Synchronization is provided in a memory system. During memory write operations a timing reference signal is transmitted with control signals to a memory device, and a calibration signal is received from the memory device. An internal clock signal is adjusted based on the calibration signal, and a data signal is then transmitted according to the internal clock. In this manner, the data is synchronized such that the data is accurately sampled according to the local clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.