Method and apparatus for pattern adjusted timing via pattern matching
US8453089B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2011 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | Oct 3, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An approach is provided for pattern adjusted timing via pattern matching. Embodiments include receiving data corresponding to a problematic layout pattern associated with at least one performance characteristic and data corresponding to an integrated circuit layout design, scanning the integrated circuit layout design for the problematic layout pattern, identifying at least one portion of the integrated circuit layout design substantially matching the problematic layout pattern, and modifying a netlist associated with the integrated circuit layout design, the modification being based on the at least one performance characteristic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.