Hierarchical variation analysis of integrated circuits
US8453102B1 · kind B1 · utility
50Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Mar 16, 2011 |
| Grant date | May 28, 2013 |
| Priority date | — |
| Expiry date | May 2, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technique assesses the impact of physical circuit variations, specification parameter variation, or process variations on clock, signal, and power network performance and through a hierarchical modeling and hierarchical Monte Carlo simulation method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.