Method of fabricating stacked chips in a semiconductor package
US8455301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2011 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Dec 7, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor package includes attaching a semiconductor substrate on a support substrate, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region that separates respective ones of the semiconductor chips. A first cutting groove is formed that has a first kerf width between first and second ones of the plurality of first semiconductor chips. A plurality of second semiconductor chips is attached to the plurality of first semiconductor chips. A molding layer is formed so as to fill the first cutting groove and a second cutting groove having a second kerf width that is less than the first kerf width is formed in the molding layer so as to form individual molding layers covering one of the plurality of first semiconductor chips and one of the plurality of second semiconductor chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.