Method of plating through wafer vias in a wafer for 3D packaging
US8455357B2 · kind B2 · utility
0Cited by
17References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2009 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Sep 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of plating via hole in a substrate includes providing a substrate having a first side and a second side and a plurality of through substrate via holes; depositing a first seed layer on the first side of the substrate; applying a foil on the first seed layer of the substrate closing the first ends of the plurality of via holes; electro-chemical plating of the second side of the substrate; and removing the foil.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.