Transistor arrangement with a first transistor and with a plurality of second transistors

US8455948B2 · kind B2 · utility

Assignee

• Infineon Technologies Austria AG · AT

Inventor

• Rolf Weis · Dresden, DE

Key dates

• Filing date: Jan 7, 2011
• Grant date: Jun 4, 2013
• Expiry date: Feb 17, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/87
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A transistor arrangement includes a first transistor having a drift region and a number of second transistors, each having a source region, a drain region and a gate electrode. The second transistors are coupled in series to form a series circuit that is coupled in parallel with the drift region of the first transistor.