Overlay mark enhancement feature
US8455982B2 · kind B2 · utility
2Cited by
9References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 29, 2012 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Feb 29, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An integrated circuit device includes a semiconductor substrate having a device region and an alignment region. A first material layer is disposed over the semiconductor substrate, and includes a device feature in the device region and a dummy feature in the alignment region. A dimension of the dummy feature is less than a dimension of an alignment detector. A second material layer is disposed over the semiconductor substrate, and includes an alignment feature in the alignment region. The alignment feature disposed over the dummy feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.