Differential data sensing
US8456197B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2011 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Nov 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0274
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A first sensing circuit has input terminals coupled to a true differential signal line and a complementary differential signal line. A second sensing circuit also has input terminals coupled to said true signal and said complementary signal. Each sensing circuit has a true signal sensing path and a complementary signal sensing path. The first sensing circuit has an imbalance that is biased towards the complementary signal sensing path, while the second sensing circuit has an imbalance that is biased towards the true signal sensing path. Outputs from the first and second sensing circuits are processed by a logic circuit producing an output signal that is indicative of whether there a sufficient differential signal for sensing has been developed between the true differential signal line and the complementary differential signal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.