Lock detector and method of detecting lock status for phase lock loop
US8456207B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2011 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Nov 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A lock detector for a PLL circuit includes a first signal counting circuit, a second signal counting circuit, a comparator, and a lock status unit. The first signal counting circuit is configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value. The second signal counting circuit is configured to determine a maximum counter value according to a second oscillating signal within each of the observation periods, and the second oscillating signal is generated in relation to the first oscillating signal. The comparator is configured to determine, for each of the observation periods, whether the maximum counter value equals the predetermined cycle value. The lock status unit is configured to generate a lock signal based on the maximum counter value being equal to the predetermined cycle value for a predetermined number of consecutive ones of the observation periods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.