Logic circuit for a semiconductor memory device, and method of managing an operation in the semiconductor memory device
US8456917B1 · kind B1 · utility
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12References
20Claims
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Key dates
| Filing date | Nov 29, 2011 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Nov 29, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17768
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic circuit for a semiconductor memory device, includes a first logic portion which stores data from a first data signal, and generates a second data signal based on the first data signal, a second logic portion which generates a first address signal and stores an address from the first address signal where data from the second data signal is to be written, and a third logic portion which generates a flag signal which indicates whether the data stored in the first logic portion is valid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.