Programmable cache access protocol to optimize power consumption and performance
US8458404B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2009 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Jul 19, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable cache and cache access protocol that can be dynamically optimized with respect to either power consumption or performance based on a monitored performance of the cache. A monitoring unit monitors cache misses, load use penalty, and/or other performance parameter, and compares the monitored values against a set of one or more predetermined thresholds. Based on the comparison results, a cache controller configures the programmable cache to operate in a parallel mode, to increase cache performance at the cost of greater power consumption, or in a serial mode, to conserve power at the cost of unnecessary performance. A banked cache memory that supports aligned and unaligned instruction fetches using a banked access strategy, and a cache access controller that includes a prefetch capability are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.