Multiple critical word bypassing in a memory controller
US8458406B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2010 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Aug 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a memory controller may be configured to transmit two or more critical words (or beats) corresponding to two or more different read requests prior to returning the remaining beats of the read requests. Such an embodiment may reduce latency to the sources of the memory requests, which may be stalled awaiting the critical words. The remaining words may fill a cache block or other buffer, but may not be required by the sources as quickly as the critical words in order to support higher performance. In some embodiments, once a remaining beat of a block is transmitted, all of the remaining beats may be transmitted contiguously. In other embodiments, additional critical words may be forwarded between remaining beats of a block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.