Error handling mechanism for a tag memory within coherency control circuitry
US8458532B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Oct 27, 2010 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Aug 23, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system 2 is provided with multiple processor cores 4, 6, 8, 10 each incorporating a data cache memory 12, 14, 16, 18. A snoop control unit 20 manages coherency between the data values stored within the data caches 12, 14, 16, 18. The snoop control unit 20 incorporates a TAG memory 22. If an error is detected within an entry of the TAG memory 22, then a hit operation is forced to the corresponding storage location one or more of the data caches 12, 14, 16, 18.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.