Latency detection in a memory built-in self-test by using a ping signal
US8458538B2 · kind B2 · utility
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7References
10Claims
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Key dates
| Filing date | Feb 22, 2010 |
| Grant date | Jun 4, 2013 |
| Priority date | — |
| Expiry date | Jan 7, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.