Method for manufacturing a transistor with parallel semiconductor nanofingers

US8460978B2 · kind B2 · utility

Assignee

• STMicroelectronics (Crolles 2) SAS · FR

Inventors

• Philippe Coronel · Barraux, FR
• Jessy Bustos · Le Touvet, FR
• Romain Wacquez · Grenoble, FR

Key dates

• Filing date: Aug 7, 2006
• Grant date: Jun 11, 2013
• Expiry date: Dec 8, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6735

Abstract

A method of producing a transistor having parallel semiconductor nanofingers. The method includes: forming a monocrystalline layer of a semiconductor material on a layer of a subjacent material which can be selectively etched in relation to the monocrystalline layer; etching parallel partitions in the monocrystalline layer and in the subjacent layer and continuing said etching operation in order to hollow out part of the subjacent layer of material; filling the gap between the partitions and the hollowed-out part with a first insulating material; defining a central part of the partitions and removing the first insulating material from around the central part of the monocrystalline layer, thereby forming a finger of semiconductor material; and filling and coating the central part with a conductor material.