Multiple surface finishes for microelectronic package substrates
US8461036B2 · kind B2 · utility
23Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2009 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Feb 26, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49222
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Multiple surface finishes are applied to a substrate for a microelectronics package by applying a first surface finish to connection pads of a first area of the substrate, masking the first area of the substrate without masking a second area of the substrate, applying a second different surface finish to connection pads of the second area of the substrate, and removing the mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.