Semiconductor device having a nonvolatile memory cell with field effect transistors
US8461642B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2009 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Oct 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
Abstract
The present invention can realize a highly-integrated semiconductor device having a MONOS type nonvolatile memory cell equipped with a split gate structure without deteriorating the reliability of the device. A memory gate electrode of a memory nMIS has a height greater by from 20 to 100 nm than that of a select gate electrode of a select nMIS so that the width of a sidewall formed over one (side surface on the side of a source region) of the side surfaces of the memory gate electrode is adjusted to a width necessary for achieving desired disturb characteristics. In addition, a gate electrode of a peripheral second nMIS has a height not greater than the height of a select gate electrode of a select nMIS to reduce the width of a sidewall formed over the side surface of the gate electrode of the peripheral second nMIS so that a shared contact hole is prevented from being filled with the sidewall.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.