ESD protection devices for SOI integrated circuit and manufacturing method thereof

US8461651B2 · kind B2 · utility

Assignee

• SHANGHAI INSTITUTE OF MICROSYSTEM AND INFORMATION TECHNOLOGY CHINESE ACADEMY OF SCIENCES · CN

Inventors

• Xiaolu Huang · Shanghai, CN
• Xing Wei · Xi'an, CN
• Xinhong Cheng · Shanghai, CN
• Jing Chen · Shanghai, CN
• Miao Zhang · Beijing, CN
• Xi Wang · Shanghai, CN

Key dates

• Filing date: Dec 16, 2010
• Grant date: Jun 11, 2013
• Expiry date: Apr 17, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/611

Abstract

The present invention discloses an ESD protection structure in a SOI CMOS circuitry. The ESD protection structure includes a variety of longitudinal (vertical) PN junction structures having significantly enlarged junction areas for current flow. The resulting devices achieve increased heavy current release capability. Processes of fabricating varieties of the ESD protection longitudinal PN junction are also disclosed. Compatibility of the disclosed fabrication processes with current SOI technology reduces implementation cost and improves the integration robustness.