Circuit and circuit method for reduction of PFD noise contribution for ADPLL
US8461886B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 20, 2011 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Oct 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL includes a PFD configured to: receive a reference clock and a feedback clock, output a first signal, which includes first phase information for a rising edge of the reference clock, and output a second signal, which includes second phase information for a rising edge of the feedback clock. The PLL includes a logic gate coupled to the PFD configured to logically combine the first and second signals to produce a pulse signal having a rising edge, which includes the first phase information, and having a falling edge, which includes the second phase information. The PLL includes a TDC coupled the logic gate configured to generate a digital timing signal, which includes timing information for a phase difference of the first and second phase information. The PLL includes a controlled oscillator coupled to the TDC configured to vary a frequency of the feedback clock from the digital timing signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.