Unified memory architecture and display controller to prevent data feed under-run
US8462141B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2007 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Jul 23, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/125
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display controller for controlling data in an isochronous display where fluctuation of data feed latency occurs, the display controller including an input memory which receives pixel data and transmits the pixel data through a main route and a secondary route; wherein pixel data is transmitted through the main route and is processed for delivery to the display in a predetermined manner; characterized in that the secondary route comprises a memory for storing a two-dimensional section of the pixel data that corresponds at least in part to the pixel data being transmitted through the main route at that time; further characterized in that the display controller includes a detector for identifying a data feed latency event and in response there to switching the transmission of the pixel data to the secondary route and processing the pixel data through secondary route for delivery to the display such that when a data feed latency event occurs the stored two-dimensional section of the pixel data from the secondary route is displayed on the display.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.