Error detection and offset cancellation during multi-wire communication
US8462891B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2009 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Feb 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4919
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.