Hierarchical order ranked simulation of electronic circuits
US8463587B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2009 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Jun 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of simulating an integrated circuit design is provided. In this method, a node order ranking of nodes in a netlist can be determined. Circuits of the netlist can then be partitioned based on the node order ranking with both static current driving and dynamic current driving schemes. A hierarchical data structure can be built based on the node order partitioning. In one embodiment, intermediate node orders can be dynamically merged for simulation optimization. Then, the circuits can be re-partitioned based on one or more merged intermediate node orders. Solving and integration can be performed using the hierarchical data structure to generate an order-ranked hierarchy engine. Analysis on the order-ranked hierarchy engine can be performed. At this point, simulation data of the IC design can be exported based on the analysis. By using this method, linear network reduction with its attendant accuracy loss is unnecessary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.