Performing mathematical and logical operations in multiple sub-cycles
US8463836B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 2005 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Aug 7, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/57
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments provide a reconfigurable IC. This IC includes a set of reconfigurable circuits for performing a mathematical operation in more than one reconfiguration cycle. To perform the mathematical operation when at least one operand has n bits, the reconfigurable circuits performs a first sub-operation on m of n bits in a first reconfiguration cycle, and a second sub-operation on p of n bits in a second reconfiguration cycle. The reconfigurable IC also includes at least one storage element for storing at least a portion of the results of the first sub-operation for use during the second reconfiguration cycle in the second sub-operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.