Out-of-order execution microprocessor with reduced store collision load replay reduction
US8464029B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2009 |
| Grant date | Jun 11, 2013 |
| Priority date | — |
| Expiry date | Mar 3, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An out-of-order execution microprocessor for reducing load instruction replay likelihood due to store collisions. A register alias table (RAT) is coupled to first and second queues of entries and generates dependencies used to determine when instructions may execute out of order. The RAT allocates an entry of the first queue and populates the allocated entry with an instruction pointer of a load instruction, when it determines that the load instruction must be replayed. The RAT allocates an entry of the second queue when it encounters a store instruction and populates the allocated entry with a dependency that identifies an instruction upon which the store instruction depends for its data. The RAT causes a subsequent instance of the load instruction to share the dependency when it encounters the subsequent instance of the load instruction and determines that its instruction pointer matches the instruction pointer of an entry of the first queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.