Patent · US Active

Instruction for enabling a processor wait state

US8464035B2 · kind B2 · utility

18Cited by

2References

24Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Martin G. Dixon · Portland, US
Scott Dion Rodgers · Hillsboro, US
Taraneh Bahrami · San Jose, US
Stephen H. Gunther · Beaverton, US
Prashant Sethi · Folsom, US
Per Hammarlund · Hillsboro, US

Key dates

Filing date	Dec 18, 2009
Grant date	Jun 11, 2013
Priority date	—
Expiry date	Dec 7, 2031

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D30/50
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In one embodiment, the present invention includes a processor having a core with decode logic to decode an instruction prescribing an identification of a location to be monitored and a timer value, and a timer coupled to the decode logic to perform a count with respect to the timer value. The processor may further include a power management unit coupled to the core to determine a type of a low power state based at least in part on the timer value and cause the processor to enter the low power state responsive to the determination. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.