DRAM with dopant stop layer and method of fabricating the same
US8466504B2 · kind B2 · utility
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2Claims
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Key dates
| Filing date | Sep 14, 2011 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | Jan 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A DRAM with dopant stop layer includes a substrate, a trench-type transistor and a capacitor electrically connected to the trench-type transistor. The trench-type transistor includes a gate structure embedded in the substrate. A source doping region and a drain doping region are disposed in the substrate at two sides of the gate structure. A boron doping region is disposed under the source doping region. A dopant stop layer is disposed within the boron doping region or below the boron doping region. The dopant stop layer includes a dopant selected from the group consisting of C, Si, Ge, Sn, Cl, F and Br.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.