Multi-level flash memory cell capable of fast programming
US8466505B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2005 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | Oct 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A semiconductor device and a method of forming the same. The semiconductor device comprises a gate structure comprising a tunnel oxide over a substrate; a floating gate over the tunnel oxide; a dielectric over the floating gate; and a control gate over the dielectric. The semiconductor device further comprises: spacers along opposite edges of the gate structure; a first impurity region doped with a first type of dopant laterally spaced apart from a first edge of the gate structure; and a second impurity region doped with a second type of dopant, opposite from the first type, the drain being substantially under the drain spacer and substantially aligned with a second edge of the gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.