Nonvolatile semiconductor memory device and method of manufacturing the same

US8466506B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventor

• Hideto TAKEKIDA · Nagoya, JP

Key dates

• Filing date: Mar 22, 2011
• Grant date: Jun 18, 2013
• Expiry date: May 24, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/30

Abstract

Nonvolatile semiconductor memory device includes; a first element isolation insulation layer within a first dummy cell region; a second element isolation insulation layer within a second dummy cell region; and a third element isolation insulation layer at boundary between the first and second dummy cell regions. Top surface of the first element isolation insulation layer is located lower than that of first floating electrode layers. Top surface of the second element isolation insulation layer is located at the same height as that of second floating electrode layers. The third element isolation insulation layer has a top surface. The end portion of the top surface adjoining the first floating electrode layer is located at a height lower than the top surface of the first floating electrode layer. The top surface of the third element isolation insulation layer has gradient ascending from the side surface of the first floating electrode layer toward that of the second floating electrode layer.