Frequency division of an input clock signal
US8466720B2 · kind B2 · utility
1Cited by
4References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 7, 2011 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | Aug 24, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/023
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuitry and method for dividing the frequency of an input clock signal for use in a prescaler of a digital frequency synthesizer. A flip flop is clocked on a first type of edge of the input clock signal, and provides an output for use as a divided clock signal. Feedback circuitry is clocked on the first type of edge of the input clock signal and provides a signal to a data input of the flip flop based on the inverse of the output of the flip flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.