Protection against fault injections of an electronic circuit with flip-flops
US8466727B2 · kind B2 · utility
3Cited by
6References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2009 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | Aug 28, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/0372
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for detecting a disturbance of the state of a synchronous flip-flop of master-slave type including two bistable circuits in series, in which the bistable circuits are triggered by two first signals different from each other, and the level of an intermediary junction point between the two bistable circuits is compared both to the level present at the input of the master-slave flip-flop and to the level present at the output, which results in two second signals providing an indication as to the presence of a possible disturbance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.