DRAM device and manufacturing method thereof

US8467220B2 · kind B2 · utility

Inventor

• Jai-Hoon Sim · Seongnam-si, KR

Key dates

• Filing date: Aug 13, 2010
• Grant date: Jun 18, 2013
• Expiry date: Oct 8, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/488

Abstract

The present invention relates to a DRAM device having 4F2 size cells and a method for fabricating the same. The DRAM device comprises plural word lines arranged parallel to each other in one direction, plural bit lines arranged parallel to each other and in an intersecting manner with the word line, and plural memory cells having a transistor and a capacitor connected electrically to a source terminal of the transistor. A gate terminal of the transistor is filling an associated trench between two adjacent memory cells in a bit line direction and simultaneously covering a sidewall of said two adjacent memory cells via a gate insulating film interposed between the gate terminal and said two adjacent memory cells. An interval between the gate terminals in the bit or the word line direction, is more distant than 1F, and the F means minimal processing size.