Microprocessor and method for deferred store data forwarding for store background data in a system with no memory model restrictions
US8468306B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2008 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | Jun 1, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipelined processor includes circuitry adapted for store forwarding, including: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one block of data; merging store data from the store request with the block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated block of data into a store data queue; for each additional store request, where the additional store request requires at least one updated block of data: determining if store forwarding is appropriate for the additional store request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the additional store request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.