Optimizing the size of memory devices used for error correction code storage
US8468433B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2012 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | Jan 26, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention are generally directed to systems, methods, and apparatuses for optimizing the size of memory devices used for error correction code storage. An apparatus (such as a memory module) may include a number of memory devices to store data and a memory device to store error correction (ECC) bits. In some embodiments, the memory devices to store data may have a density of N and the memory device to store ECC bits has a density of ½ N.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.