Method for high volume e-beam lithography
US8468473B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2012 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | Jun 8, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/31771
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The present disclosure describes a method of forming a pattern by an electron beam lithography system. The method includes receiving an integrated circuit (IC) design layout data having a polygon and a forbidden pattern, modifying the polygon and the forbidden pattern using an electron proximity correction (EPC) technique, stripping the modified polygon into subfields, converting the stripped polygon to an electron beam writer format data, and writing the electron beam writer formatted polygon onto a substrate by an electron beam writer. Stripping the modified polygon includes finding the modified forbidden pattern as a reference layer, and stitching the modified polygon to avoid stitching the modified forbidden pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.