Modeling and simulating the impact of imperfectly patterned via arrays on integrated circuits
US8468482B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2011 |
| Grant date | Jun 18, 2013 |
| Priority date | — |
| Expiry date | May 3, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique models and simulates the impact of imperfectly patterned via arrays on integrated circuits through the use of hierarchical models and a hierarchical circuit simulator. Through the hierarchical modeling and simulation approach discussed here, far more accurate electrical simulation and verification of networks is enabled for; performance, yield, and reliability. The approach further enables simulation of the effects of via process variations on large-scale circuit response. In an implementation, each via in a layout or in a via array is modeled as having an independent size from other vias based upon calibrated process simulation. The electrical characteristics of independent vias and via arrays are modeled and compiled into a reusable hierarchical distributed resistance via model. Hierarchical simulation is performed using these hierarchical distributed via models and enables more accurate results than traditional approaches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.