Silicide method
US8470707B2 · kind B2 · utility
2Cited by
0References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2011 |
| Grant date | Jun 25, 2013 |
| Priority date | — |
| Expiry date | Nov 2, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/015
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming an integrated circuit with reduced sidewall spacers to enable improved silicide formation between minimum spaced transistor gates. A process for forming an integrated circuit with reduced sidewall spacers by first forming sidewall spacer by etching a sidewall dielectric and stopping on an etch stop layer, implanting source and drain dopants self aligned to the sidewall spacers, followed by removing a portion of the sidewall dielectric and removing the etch stop layer self aligned to the reduced sidewall spacers prior to forming silicide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.